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Multiplexer behavioural

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_VHDL is
port
(
a, b, c, d, e, f, g, h : in std_logic;
Sel : in std_logic_vector(2 downto 0);

Output : out std_logic
);
end entity Multiplexer_VHDL;

architecture Behavioral of Multiplexer_VHDL is
begin
process (a, b, c, d, e, f, g, h, Sel) is
begin
case Sel is
when "000" => Output <= a;
when "001" => Output <= b;
when "010" => Output <= c;
when "011" => Output <= d;
when "100" => Output <= e;
when "101" => Output <= f;
when "110" => Output <= g;
when others => Output <= h;
end case;
end process;
end architecture Behavioral;

Posted by rummy Monday, September 27, 2010 at 5:55 AM 0 comments Labels: ,  

Multiplexer behavioural

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_VHDL is
port
(
a, b, c, d, e, f, g, h : in std_logic;
Sel : in std_logic_vector(2 downto 0);

Output : out std_logic
);
end entity Multiplexer_VHDL;

architecture Behavioral of Multiplexer_VHDL is
begin
process (a, b, c, d, e, f, g, h, Sel) is
begin
case Sel is
when "000" => Output <= a;
when "001" => Output <= b;
when "010" => Output <= c;
when "011" => Output <= d;
when "100" => Output <= e;
when "101" => Output <= f;
when "110" => Output <= g;
when others => Output <= h;
end case;
end process;
end architecture Behavioral;

Posted by rummy at 5:55 AM 0 comments Labels: ,  

4 bit comparator -behavioural

--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--entity declaration with port definitions
entity compare is
port( num1 : in std_logic_vector(3 downto 0); --input 1
num2 : in std_logic_vector(3 downto 0); --input 2
less : out std_logic; -- indicates first number is small
equal : out std_logic; -- both are equal
greater : out std_logic -- indicates first number is bigger
);
end compare;

--architecture of entity
architecture Behavioral of compare is

begin
process(num1,num2)
begin -- process starts with a 'begin' statement
if (num1 > num2 ) then --checking whether num1 is greater than num2
less <= '0';
equal <= '0';
greater <= '1';
elsif (num1 < num2) then --checking whether num1 is less than num2
less <= '1';
equal <= '0';
greater <= '0';
else --checking whether num1 is equal to num2
less <= '0';
equal <= '1';
greater <= '0';
end if;
end process; -- process ends with a 'end process' statement

end Behavioral;

Posted by rummy at 5:54 AM 0 comments Labels: ,  

rs flip flop

library ieee;
use ieee.std_logic_1164.all;
entity rsflipflop is
port(r,s,clk:in std_logic;
q,q1:inout std_logic);
end rsflipflop;
architecture archi_rs of rsflipflop is
begin
process(clk)
begin
if(clk 'event and clk='1')then
if(r='0' and s='0') then q<=q;q1<=(not q);
else if(r='0' and s='1') then q<='1';q1<='0';
else if(r='1' and s='0') then q<='0';q1<='1';
else if(r='1' and s='1') then q<='0';q1<='0';
end if;
end if;
end if;
end if;
end if;
end process;
end archi_rs;

Posted by rummy Sunday, September 26, 2010 at 5:54 AM 0 comments Labels:  

Shift register

library ieee;
use ieee.std_logic_1164.all;
Entity shiftregister is
port(a1,b1,c1,d1,mc,si,clk1,clk2:in std_logic;
a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,qa,qb,qc,qa1,qb1,qc1,qd1,qd:inout std_logic);

end shiftregister;

architecture arch_shiftregister of shiftregister is




component and_gate
port(a,b:in std_logic;c:out std_logic);
end component;

component not_gate
port(a :in std_logic;b:out std_logic);
end component;

component nor_gate
port(a,b:in std_logic;c:out std_logic);
end component;

component or_gate
port(a,b:in std_logic;c:out std_logic);
end component;


component rsflipflop
port(r,s,clk:in std_logic;
q,q1:inout std_logic);
end component;



begin

l1: and_gate port map(si,a,c);
l2: and_gate port map(b,a1,d);
l3: and_gate port map(qa,a,e);
l4: and_gate port map(b,b1,f);
l5: and_gate port map(qb,a,g);
l6: and_gate port map(b,c1,h);
l7: and_gate port map(qc,a,i);
l8: and_gate port map(b,d1,j);
l9: and_gate port map(a,clk1,o);
l10: and_gate port map(mc,clk2,p);
l11: not_gate port map(mc,a);
l12: not_gate port map(a,b);
l13: nor_gate port map(c,d,k);
l14: nor_gate port map(e,f,l);
l15: nor_gate port map(g,h,m);
l16: nor_gate port map(i,j,n);
l17: or_gate port map(o,p,u);
l18: rsflipflop port map(k,q,u,qa,qa1);
l19: rsflipflop port map(l,r,u,qb,qb1);
l20: rsflipflop port map(m,s,u,qc,qc1);
l21: rsflipflop port map(n,t,u,qd,qd1);
l22: not_gate port map(k,q);
l23: not_gate port map(l,r);
l24: not_gate port map(m,s);
l25: not_gate port map(n,t);

end arch_shiftregister;





Posted by rummy at 5:54 AM 0 comments Labels:  

4bit comparator

library ieee;
use ieee.std_logic_1164.all;
Entity comparator is
port(A0,B0,A1,B1,A2,B2,A3,B3,I0,I1,I2:in std_logic;y0,y1,y2:out std_logic);
end comparator;
architecture arch_comparator of comparator is
signal c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z,ta,tb,tc,td:std_logic;

component nand_gate
port(a,b:in std_logic; c: out std_logic);
end component;

component and_gate
port(a,b:in std_logic; c: out std_logic);
end component;


component nor_gate
port(a,b:in std_logic; c: out std_logic);
end component;

component fouripand_gate
port(a,b,c,d:in std_logic; e:out std_logic);
end component;


component fiveand_gate
port(a,b,c,d,e:in std_logic; f:out std_logic);
end component;

component sixnorgate
port(a,b,c,d,e,f:in std_logic; g:out std_logic);
end component;

component threeipand_gate
port(a,b,c :in std_logic;d:out std_logic);
end component;

begin


l1: nand_gate port map(A3,B3,c);
l2: nand_gate port map(A2,B2,s);
l3: nand_gate port map(A1,B1,w);
l4: nand_gate port map(A0,B0,ta);
l5: and_gate port map(A3,c,d);
l6: and_gate port map(c,B3,e);
l7: and_gate port map(A2,s,t);
l8: and_gate port map(s,B2,u);
l9: and_gate port map(A1,w,x);
l10: and_gate port map(w,B1,y);
l11: and_gate port map(A0,ta,tb);
l12: and_gate port map(ta,B0,tc);
l13: and_gate port map(B3,c,g);
l14: and_gate port map(c,A3,r);
l15: nor_gate port map(d,e,f);
l16: nor_gate port map(t,u,v);
l17: nor_gate port map(x,y,z);
l18: nor_gate port map(tb,tc,td);
l19: threeipand_gate port map(B2,s,f,h);
l20: threeipand_gate port map(s,A2,f,q);
l21: fouripand_gate port map(B1,w,f,v,i);
l22: fouripand_gate port map(f,v,w,A1,p);
l23: fiveand_gate port map(f,v,z,td,I0,k);
l24: fiveand_gate port map(f,v,z,td,I1,l);
l25: fiveand_gate port map(f,v,z,td,I1,y1);
l26: fiveand_gate port map(f,v,z,td,I1,m);
l27: fiveand_gate port map(f,v,z,td,I2,n);
l28: fiveand_gate port map(f,v,z,ta,A0,o);
l29: fiveand_gate port map(f,v,z,ta,B0,j);
l30: sixnorgate port map(g,h,i,j,k,l,y0);
l31: sixnorgate port map(m,n,o,p,q,r,y2);

end arch_comparator;


Posted by rummy at 5:53 AM 0 comments Labels:  

half subracter

library ieee;
use ieee.std_logic_1164.all;
Entity halfsubtractor_gate is
port(a,b:in std_logic;sum,difference:out std_logic);
end halfsubtractor_gate;
architecture design of halfsubtractor_gate is
begin
sum<=(not a and b);
difference<=(a and not b);
end design;




Posted by rummy at 5:52 AM 0 comments Labels:  

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