JK flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK_Flipflop is
port ( clk: in std_logic;
J, K:in std_logic;
Q, Qbar: out std_logic;
reset: in std_logic
);
end JK_Flipflop;
architecture Behavioral of JK_Flipflop is
signal qtemp,qbartemp : std_logic :='0';
begin
Q <= qtemp;
Qbar <= qbartemp;
process(clk,reset)
begin
if(reset = '1') then
qtemp <= '0';
qbartemp <= '1';
elsif( rising_edge(clk) ) then
if(J='0' and K='0') then
NULL;
elsif(J='0' and K='1') then
qtemp <= '0';
qbartemp <= '1';
elsif(J='1' and K='0') then
qtemp <= '1';
qbartemp <= '0';
else
qtemp <= not qtemp;
qbartemp <= not qbartemp;
end if;
end if;
end process;
end Behavioral;

decimal counter

library ieee;
use ieee.std_logic_1164.all;
entity ic7490 is
port(ms1,ms2,mr1,mr2,clk:in std_logic;
q:inout std_logic_vector(3 downto 0));
end ic7490;
architecture ic7490_arch of ic7490 is
component nand2
port(a,b:in std_logic; c:out std_logic);
end component;
component and2
port(a,b:in std_logic; c:out std_logic);
end component;
component JK_Flipflop
port(j,k,clk,reset:in std_logic;
q,qbar:inout std_logic);
end component;
signal ms,mr,a2:std_logic;
signal q_l:std_logic_vector(3 downto 0);
signal j,k:std_logic:='1';
begin
L1:nand2 port map(ms1,ms2,ms);
L2:nand2 port map(mr1,mr2,mr);
L3:and2 port map(q(1),q(2),a2);
L6:JK_Flipflop port map(j,k,clk,mr,q(0),q_l(0));
L7:JK_Flipflop port map(q_l(3),k,q_l(0),mr,q(1),q_l(1));
L8:JK_Flipflop port map(j,k,q_l(1),mr,q(2),q_l(2));
L9:JK_Flipflop port map(a2,k,q_l(0),mr,q(3),q_l(3));
end ic7490_arch;

decoder

library ieee;
use ieee.std_logic_1164.all;
entity Decoder is
port(g1,g2,g3:in std_logic;
s : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0));
end Decoder;
architecture Behavioral of Decoder is
signal y_s : std_logic_vector(7 downto 0);
begin
process(s,g1,g2,g3,y_s)
begin
case s is
when "000" => y_s <="11111110" ;
when "001" => y_s <="11111101" ;
when "010" => y_s <="11111011" ;
when "011" => y_s <="11110111" ;
when "100" => y_s <="11101111" ;
when "101" => y_s <="11011111" ;
when "110" => y_s <="10111111" ;
when "111" => y_s <="01111111" ;
when others=> y_s <="11111111";
end case ;
if (g1 and not g2 and not g3)='1' then y<=y_s;
else y<="11111111";
end if ;
end process;
end Behavioral;