decimal counter

library ieee;
use ieee.std_logic_1164.all;
entity ic7490 is
port(ms1,ms2,mr1,mr2,clk:in std_logic;
q:inout std_logic_vector(3 downto 0));
end ic7490;
architecture ic7490_arch of ic7490 is
component nand2
port(a,b:in std_logic; c:out std_logic);
end component;
component and2
port(a,b:in std_logic; c:out std_logic);
end component;
component JK_Flipflop
port(j,k,clk,reset:in std_logic;
q,qbar:inout std_logic);
end component;
signal ms,mr,a2:std_logic;
signal q_l:std_logic_vector(3 downto 0);
signal j,k:std_logic:='1';
begin
L1:nand2 port map(ms1,ms2,ms);
L2:nand2 port map(mr1,mr2,mr);
L3:and2 port map(q(1),q(2),a2);
L6:JK_Flipflop port map(j,k,clk,mr,q(0),q_l(0));
L7:JK_Flipflop port map(q_l(3),k,q_l(0),mr,q(1),q_l(1));
L8:JK_Flipflop port map(j,k,q_l(1),mr,q(2),q_l(2));
L9:JK_Flipflop port map(a2,k,q_l(0),mr,q(3),q_l(3));
end ic7490_arch;