decoder

library ieee;
use ieee.std_logic_1164.all;
entity Decoder is
port(g1,g2,g3:in std_logic;
s : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0));
end Decoder;
architecture Behavioral of Decoder is
signal y_s : std_logic_vector(7 downto 0);
begin
process(s,g1,g2,g3,y_s)
begin
case s is
when "000" => y_s <="11111110" ;
when "001" => y_s <="11111101" ;
when "010" => y_s <="11111011" ;
when "011" => y_s <="11110111" ;
when "100" => y_s <="11101111" ;
when "101" => y_s <="11011111" ;
when "110" => y_s <="10111111" ;
when "111" => y_s <="01111111" ;
when others=> y_s <="11111111";
end case ;
if (g1 and not g2 and not g3)='1' then y<=y_s;
else y<="11111111";
end if ;
end process;
end Behavioral;