counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK_Flipflop is
port ( clk: in std_logic;
J, K:in std_logic;
Q, Qbar: out std_logic;
reset: in std_logic
);
end JK_Flipflop;
architecture Behavioral of JK_Flipflop is
signal qtemp,qbartemp : std_logic :='0';
begin
Q <= qtemp;
Qbar <= qbartemp;
process(clk,reset)
begin
if(reset = '1') then
qtemp <= '0';
qbartemp <= '1';
elsif( rising_edge(clk) ) then
if(J='0' and K='0') then
NULL;
elsif(J='0' and K='1') then
qtemp <= '0';
qbartemp <= '1';
elsif(J='1' and K='0') then
qtemp <= '1';
qbartemp <= '0';
else
qtemp <= not qtemp;
qbartemp <= not qbartemp;
end if;
end if;
end process;
end Behavioral;

JK flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF_VHDL is
port( J,K: in std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end JK_FF_VHDL;

architecture Behavioral of JK_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if Clock'event and Clock='1' then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;

3 to 8 Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Decoder is
port
(
Sel : in std_logic_vector(2 downto 0);

y : out std_logic_vector(7 downto 0)
);
end entity Decoder;

architecture Behavioral of Decoder is
begin
y <= "00000001" when Sel="000" else
"00000010" when Sel="001" else
"00000100" when Sel="010" else
"00001000" when Sel="011" else
"00010000" when Sel="100" else
"00100000" when Sel="101" else
"01000000" when Sel="110" else
"10000000";
end architecture Behavioral;

d flipflop behavoiral

library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (
d,clk,rd,sd : in STD_LOGIC;
q ,q1: inout STD_LOGIC);
end dff;
architecture dffarch of dff is
begin
process(d,clk)
begin
if (rd='1'and sd='0') then
q <= '1';q1<= '0';
elsif (rd='0'and sd='1') then
q <= '0';q1<= '1';
elsif (sd='0'and rd='0')then
q<='1';q1<='1'; end if;
if (sd='1'and rd='1')then
if clk'event and clk='1' then
q <= d ;q1 <= not d;
end if;
end if;
end process;
end dffarch;

Multiplexer behavioural

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_VHDL is
port
(
a, b, c, d, e, f, g, h : in std_logic;
Sel : in std_logic_vector(2 downto 0);

Output : out std_logic
);
end entity Multiplexer_VHDL;

architecture Behavioral of Multiplexer_VHDL is
begin
process (a, b, c, d, e, f, g, h, Sel) is
begin
case Sel is
when "000" => Output <= a;
when "001" => Output <= b;
when "010" => Output <= c;
when "011" => Output <= d;
when "100" => Output <= e;
when "101" => Output <= f;
when "110" => Output <= g;
when others => Output <= h;
end case;
end process;
end architecture Behavioral;

Multiplexer behavioural

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_VHDL is
port
(
a, b, c, d, e, f, g, h : in std_logic;
Sel : in std_logic_vector(2 downto 0);

Output : out std_logic
);
end entity Multiplexer_VHDL;

architecture Behavioral of Multiplexer_VHDL is
begin
process (a, b, c, d, e, f, g, h, Sel) is
begin
case Sel is
when "000" => Output <= a;
when "001" => Output <= b;
when "010" => Output <= c;
when "011" => Output <= d;
when "100" => Output <= e;
when "101" => Output <= f;
when "110" => Output <= g;
when others => Output <= h;
end case;
end process;
end architecture Behavioral;

4 bit comparator -behavioural

--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--entity declaration with port definitions
entity compare is
port( num1 : in std_logic_vector(3 downto 0); --input 1
num2 : in std_logic_vector(3 downto 0); --input 2
less : out std_logic; -- indicates first number is small
equal : out std_logic; -- both are equal
greater : out std_logic -- indicates first number is bigger
);
end compare;

--architecture of entity
architecture Behavioral of compare is

begin
process(num1,num2)
begin -- process starts with a 'begin' statement
if (num1 > num2 ) then --checking whether num1 is greater than num2
less <= '0';
equal <= '0';
greater <= '1';
elsif (num1 < num2) then --checking whether num1 is less than num2
less <= '1';
equal <= '0';
greater <= '0';
else --checking whether num1 is equal to num2
less <= '0';
equal <= '1';
greater <= '0';
end if;
end process; -- process ends with a 'end process' statement

end Behavioral;

rs flip flop

library ieee;

use ieee.std_logic_1164.all;

entity rsflipflop is

port(r,s,clk:in std_logic;

q,q1:inout std_logic);

end rsflipflop;

architecture archi_rs of rsflipflop is

begin

process(clk)

begin

if(clk 'event and clk='1')then

if(r='0' and s='0') then q<=q;q1<=(not q);

else if(r='0' and s='1') then q<='1';q1<='0';

else if(r='1' and s='0') then q<='0';q1<='1';

else if(r='1' and s='1') then q<='0';q1<='0';

end if;

end if;

end if;

end if;

end if;

end process;

end archi_rs;

Shift register

library ieee;

use ieee.std_logic_1164.all;

Entity shiftregister is

port(a1,b1,c1,d1,mc,si,clk1,clk2:in std_logic;

a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,qa,qb,qc,qa1,qb1,qc1,qd1,qd:inout std_logic);

end shiftregister;

architecture arch_shiftregister of shiftregister is

component and_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component not_gate

port(a :in std_logic;b:out std_logic);

end component;

component nor_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component or_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component rsflipflop

port(r,s,clk:in std_logic;

q,q1:inout std_logic);

end component;

begin

l1: and_gate port map(si,a,c);

l2: and_gate port map(b,a1,d);

l3: and_gate port map(qa,a,e);

l4: and_gate port map(b,b1,f);

l5: and_gate port map(qb,a,g);

l6: and_gate port map(b,c1,h);

l7: and_gate port map(qc,a,i);

l8: and_gate port map(b,d1,j);

l9: and_gate port map(a,clk1,o);

l10: and_gate port map(mc,clk2,p);

l11: not_gate port map(mc,a);

l12: not_gate port map(a,b);

l13: nor_gate port map(c,d,k);

l14: nor_gate port map(e,f,l);

l15: nor_gate port map(g,h,m);

l16: nor_gate port map(i,j,n);

l17: or_gate port map(o,p,u);

l18: rsflipflop port map(k,q,u,qa,qa1);

l19: rsflipflop port map(l,r,u,qb,qb1);

l20: rsflipflop port map(m,s,u,qc,qc1);

l21: rsflipflop port map(n,t,u,qd,qd1);

l22: not_gate port map(k,q);

l23: not_gate port map(l,r);

l24: not_gate port map(m,s);

l25: not_gate port map(n,t);

end arch_shiftregister;

4bit comparator

library ieee;

use ieee.std_logic_1164.all;

Entity comparator is

port(A0,B0,A1,B1,A2,B2,A3,B3,I0,I1,I2:in std_logic;y0,y1,y2:out std_logic);

end comparator;

architecture arch_comparator of comparator is

signal c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z,ta,tb,tc,td:std_logic;

component nand_gate

port(a,b:in std_logic; c: out std_logic);

end component;

component and_gate

port(a,b:in std_logic; c: out std_logic);

end component;

component nor_gate

port(a,b:in std_logic; c: out std_logic);

end component;

component fouripand_gate

port(a,b,c,d:in std_logic; e:out std_logic);

end component;

component fiveand_gate

port(a,b,c,d,e:in std_logic; f:out std_logic);

end component;

component sixnorgate

port(a,b,c,d,e,f:in std_logic; g:out std_logic);

end component;

component threeipand_gate

port(a,b,c :in std_logic;d:out std_logic);

end component;

begin

l1: nand_gate port map(A3,B3,c);

l2: nand_gate port map(A2,B2,s);

l3: nand_gate port map(A1,B1,w);

l4: nand_gate port map(A0,B0,ta);

l5: and_gate port map(A3,c,d);

l6: and_gate port map(c,B3,e);

l7: and_gate port map(A2,s,t);

l8: and_gate port map(s,B2,u);

l9: and_gate port map(A1,w,x);

l10: and_gate port map(w,B1,y);

l11: and_gate port map(A0,ta,tb);

l12: and_gate port map(ta,B0,tc);

l13: and_gate port map(B3,c,g);

l14: and_gate port map(c,A3,r);

l15: nor_gate port map(d,e,f);

l16: nor_gate port map(t,u,v);

l17: nor_gate port map(x,y,z);

l18: nor_gate port map(tb,tc,td);

l19: threeipand_gate port map(B2,s,f,h);

l20: threeipand_gate port map(s,A2,f,q);

l21: fouripand_gate port map(B1,w,f,v,i);

l22: fouripand_gate port map(f,v,w,A1,p);

l23: fiveand_gate port map(f,v,z,td,I0,k);

l24: fiveand_gate port map(f,v,z,td,I1,l);

l25: fiveand_gate port map(f,v,z,td,I1,y1);

l26: fiveand_gate port map(f,v,z,td,I1,m);

l27: fiveand_gate port map(f,v,z,td,I2,n);

l28: fiveand_gate port map(f,v,z,ta,A0,o);

l29: fiveand_gate port map(f,v,z,ta,B0,j);

l30: sixnorgate port map(g,h,i,j,k,l,y0);

l31: sixnorgate port map(m,n,o,p,q,r,y2);

end arch_comparator;

half subracter

library ieee;

use ieee.std_logic_1164.all;

Entity halfsubtractor_gate is

port(a,b:in std_logic;sum,difference:out std_logic);

end halfsubtractor_gate;

architecture design of halfsubtractor_gate is

begin

sum<=(not a and b);

difference<=(a and not b);

end design;

full adder struct

library ieee;

use ieee.std_logic_1164.all;

Entity fulladderstruct_gate is

port(m,n,l:in std_logic; d,e,f:inout std_logic; s,o:out std_logic);

end fulladderstruct_gate;

architecture fulladder_arch of fulladderstruct_gate is

component xor_gate

port(a,b : in std_logic; c:out std_logic);

end component;

component and_gate

port(a,b : in std_logic; c:out std_logic);

end component;

component or_gate

port(a,b : in std_logic; c:out std_logic);

end component;

begin

u1: and_gate port map( a=>m, b=>n, c=>e );

u2: and_gate port map( a=>d, b=>l, c=>f );

u3: xor_gate port map( a=>m, b=>n, c=>d );

u4: xor_gate port map( a=>d, b=>l, c=>s );

u5: or_gate port map( a=>f, b=>e, c=>o );

end fulladder_arch;

half adder

library ieee;

use ieee.std_logic_1164.all;

Entity halfadder_gate is

port(m,n:in std_logic;o,s:out std_logic);

end halfadder_gate;

architecture design of halfadder_gate is

component xor_gate

port(a,b : in std_logic; c:out std_logic);

end component;

component and_gate

port(a,b : in std_logic; c:out std_logic);

end component;

begin

u1: and_gate port map( a=>m,b=>n,c=>s );

u2: xor_gate port map( a=>m,b=>n,c=>o );

end design;

dflipflop

library ieee;

use ieee.std_logic_1164.all;

Entity dflipflop is

port(SD,Rd,CD,D:in std_logic;

q0,q1: inout std_logic);

end dflipflop;

architecture arch_d of dflipflop is

signal a,b,c,e:std_logic;

component threeipnand_gate

port(a,b,c :in std_logic;d:out std_logic);

end component;

begin

l1: threeipnand_gate port map(SD,e,b,a);

l2: threeipnand_gate port map(a,RD,CD,b);

l3: threeipnand_gate port map(b,CD,e,c);

l4: threeipnand_gate port map(c,RD,D,e);

l5: threeipnand_gate port map(SD,b,q1,q0);

l6: threeipnand_gate port map(q0,RD,c,q1);

end arch_d;

Multiplexer

library ieee;

use ieee.std_logic_1164.all;

Entity eightone is

port(EN1,d1,d2,d3,d4,d5,d6,d7,d8,s0,s1,s2:in std_logic;

y:inout std_logic;

y_l:out std_logic);

end eightone;

architecture arch_eight of eightone is

signal m,n,l,en,y0,y1,y2,y3,y4,y5,y6,y7:std_logic;

component fiveand_gate

port(a,b,c,d,e :in std_logic;f:out std_logic);

end component;

component not_gate

port(a :in std_logic;b:out std_logic);

end component;

component eightnorgate

port(a,b,c,d,e,f,h,i :in std_logic;g:out std_logic);

end component;

begin

l1: not_gate port map(s0,l);

l2: not_gate port map(s1,m);

l3: not_gate port map(s2,n);

l4: not_gate port map(EN1,en);

l6: fiveand_gate port map(m,d1,n,l,en,y0);

l7: fiveand_gate port map(m,d2,n,l,en,y1);

l8: fiveand_gate port map(m,d3,s0,s1,en,y2);

l9: fiveand_gate port map(m,d4,s0,s1,en,y3);

l10: fiveand_gate port map(d5,s2,l,m,en,y4);

l11: fiveand_gate port map(d6,s2,l,m,en,y5);

l12: fiveand_gate port map(d7,s0,s2,l,en,y6);

l13: fiveand_gate port map(d8,s0,s1,s2,en,y7);

l14: eightnorgate port map(y0,y1,y2,y3,y4,y5,y6,y7,y);

l15: not_gate port map(y,y_l);

end arch_eight;

demultiplexer

library ieee;

use ieee.std_logic_1164.all;

Entity oneeight is

port(a,b,tc,tg,uc,ug:in std_logic;

ty0,ty1,ty2,ty3,uy0,uy1,uy2,uy3:out std_logic);

end oneeight;

architecture arch_eight of oneeight is

signal p,q,r,x,y,a1,b1:std_logic;

component and_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component not_gate

port(a :in std_logic;b:out std_logic);

end component;

component threeipnand_gate

port(a,b,c:in std_logic;d:out std_logic);

end component;

begin

l1: not_gate port map(tg,p);

l2: not_gate port map(uc,q);

l3: not_gate port map(ug,r);

l4: not_gate port map(a,a1);

l5: not_gate port map(b,b1);

l6: and_gate port map(tc,q,x);

l7: and_gate port map(uc,r,y);

l8: threeipnand_gate port map(a1,b1,x,ty0);

l9: threeipnand_gate port map(a,b1,x,ty1);

l10: threeipnand_gate port map(a1,b,x,ty2);

l11: threeipnand_gate port map(a,b,x,ty3);

l12: threeipnand_gate port map(a1,b1,y,uy0);

l13: threeipnand_gate port map(a,b1,y,uy1);

l14: threeipnand_gate port map(a1,b,y,uy2);

l15: threeipnand_gate port map(a,b,y,uy3);

end arch_eight;

3-8 decoder

library ieee;

use ieee.std_logic_1164.all;

Entity three_eight is

port(A,B,C,E1,E2,E3:in std_logic;y0,y1,y2,y3,y4,y5,y6,y7:out std_logic);

end three_eight;

architecture decoder of three_eight is

signal g,f,n,j,i,h,m,l,k:std_logic;

component not_gate

port(a:in std_logic; b: out std_logic);

end component;

component fouripnand_gate

port(a,b,c,d:in std_logic; e:out std_logic);

end component;

component threeipand_gate

port(a,b,c :in std_logic;d:out std_logic);

end component;

begin

l1: not_gate port map(E2,g);

l2: not_gate port map(E2,f);

l3: not_gate port map(A,j);

l4: not_gate port map(B,i);

l5: not_gate port map(C,h);

l6: not_gate port map(j,m);

l7: not_gate port map(i,l);

l8: not_gate port map(h,k);

l9: threeipand_gate port map(E1,g,f,n);

l10: fouripnand_gate port map(n,h,i,j,y0);

l11: fouripnand_gate port map(i,h,m,n,y1);

l12: fouripnand_gate port map(n,h,l,j,y2);

l13: fouripnand_gate port map(h,m,l,n,y3);

l14: fouripnand_gate port map(j,i,k,n,y4);

l15: fouripnand_gate port map(i,k,m,n,y5);

l16: fouripnand_gate port map(i,j,k,n,y6);

l17: fouripnand_gate port map(n,l,k,m,y7);

end decoder;

4 nand gate

library ieee;

use ieee.std_logic_1164.all;

Entity fouripnand_gate is

port(a,b,c,d:in std_logic;e:out std_logic);

end fouripnand_gate;

architecture design of fouripnand_gate is

begin

e<= (not(a and b and c and d));

end design;

4 and gate

library ieee;

use ieee.std_logic_1164.all;

Entity fouripand_gate is

port(a,b,c,d:in std_logic;e:out std_logic);

end fouripand_gate;

architecture design of fouripand_gate is

begin

e<=(a and b and c and d);

end design;

5 and gate

library ieee;

use ieee.std_logic_1164.all;

Entity fiveand_gate is

port(a,b,c,d,e:in std_logic;f:out std_logic);

end fiveand_gate;

architecture design of fiveand_gate is

begin

f<=(a and b and c and d and e);

end design;

six nor

library ieee;

use ieee.std_logic_1164.all;

Entity sixnorgate is

port(a,b,c,d,e,f:in std_logic;g:out std_logic);

end sixnorgate;

architecture design of sixnorgate is

begin

g<=not(a or b or c or d or e or f);

end design;

Nand gate

library ieee;

use ieee.std_logic_1164.all;

Entity nand_gate is

port(a,b:in std_logic;c:out std_logic);

end nand_gate;

architecture design of nand_gate is

begin

c<=(not(a and b));

end design;

Not gate

library ieee;

use ieee.std_logic_1164.all;

Entity not_gate is

port(a:in std_logic;b:out std_logic);

end not_gate;

architecture design of not_gate is

begin

b<= (not a );

end design;

nor gate

library ieee;

use ieee.std_logic_1164.all;

Entity nor_gate is

port(a,b:in std_logic;c:out std_logic);

end nor_gate;

architecture design of nor_gate is

begin

c<=(a nor b);

end design;

Or gate

library ieee;

use ieee.std_logic_1164.all;

Entity or_gate is

port(a,b:in std_logic;c:out std_logic);

end or_gate;

architecture design of or_gate is

begin

c<=(a or b);

end design;

Basic And gate

library ieee;

use ieee.std_logic_1164.all;

Entity and_gate is

port(a,b:in std_logic;c:out std_logic);

end and_gate;

architecture design of and_gate is

begin

c<=(a and b);

end design;