full adder struct

library ieee;

use ieee.std_logic_1164.all;

Entity fulladderstruct_gate is

port(m,n,l:in std_logic; d,e,f:inout std_logic; s,o:out std_logic);

end fulladderstruct_gate;

architecture fulladder_arch of fulladderstruct_gate is

component xor_gate

port(a,b : in std_logic; c:out std_logic);

end component;

component and_gate

port(a,b : in std_logic; c:out std_logic);

end component;

component or_gate

port(a,b : in std_logic; c:out std_logic);

end component;

begin

u1: and_gate port map( a=>m, b=>n, c=>e );

u2: and_gate port map( a=>d, b=>l, c=>f );

u3: xor_gate port map( a=>m, b=>n, c=>d );

u4: xor_gate port map( a=>d, b=>l, c=>s );

u5: or_gate port map( a=>f, b=>e, c=>o );

end fulladder_arch;