half adder

library ieee;

use ieee.std_logic_1164.all;

Entity halfadder_gate is

port(m,n:in std_logic;o,s:out std_logic);

end halfadder_gate;

architecture design of halfadder_gate is

component xor_gate

port(a,b : in std_logic; c:out std_logic);

end component;

component and_gate

port(a,b : in std_logic; c:out std_logic);

end component;

begin

u1: and_gate port map( a=>m,b=>n,c=>s );

u2: xor_gate port map( a=>m,b=>n,c=>o );

end design;