demultiplexer

library ieee;

use ieee.std_logic_1164.all;

Entity oneeight is

port(a,b,tc,tg,uc,ug:in std_logic;

ty0,ty1,ty2,ty3,uy0,uy1,uy2,uy3:out std_logic);

end oneeight;

architecture arch_eight of oneeight is

signal p,q,r,x,y,a1,b1:std_logic;

component and_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component not_gate

port(a :in std_logic;b:out std_logic);

end component;

component threeipnand_gate

port(a,b,c:in std_logic;d:out std_logic);

end component;

begin

l1: not_gate port map(tg,p);

l2: not_gate port map(uc,q);

l3: not_gate port map(ug,r);

l4: not_gate port map(a,a1);

l5: not_gate port map(b,b1);

l6: and_gate port map(tc,q,x);

l7: and_gate port map(uc,r,y);

l8: threeipnand_gate port map(a1,b1,x,ty0);

l9: threeipnand_gate port map(a,b1,x,ty1);

l10: threeipnand_gate port map(a1,b,x,ty2);

l11: threeipnand_gate port map(a,b,x,ty3);

l12: threeipnand_gate port map(a1,b1,y,uy0);

l13: threeipnand_gate port map(a,b1,y,uy1);

l14: threeipnand_gate port map(a1,b,y,uy2);

l15: threeipnand_gate port map(a,b,y,uy3);

end arch_eight;