Shift register

library ieee;

use ieee.std_logic_1164.all;

Entity shiftregister is

port(a1,b1,c1,d1,mc,si,clk1,clk2:in std_logic;

a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,qa,qb,qc,qa1,qb1,qc1,qd1,qd:inout std_logic);

end shiftregister;

architecture arch_shiftregister of shiftregister is

component and_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component not_gate

port(a :in std_logic;b:out std_logic);

end component;

component nor_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component or_gate

port(a,b:in std_logic;c:out std_logic);

end component;

component rsflipflop

port(r,s,clk:in std_logic;

q,q1:inout std_logic);

end component;

begin

l1: and_gate port map(si,a,c);

l2: and_gate port map(b,a1,d);

l3: and_gate port map(qa,a,e);

l4: and_gate port map(b,b1,f);

l5: and_gate port map(qb,a,g);

l6: and_gate port map(b,c1,h);

l7: and_gate port map(qc,a,i);

l8: and_gate port map(b,d1,j);

l9: and_gate port map(a,clk1,o);

l10: and_gate port map(mc,clk2,p);

l11: not_gate port map(mc,a);

l12: not_gate port map(a,b);

l13: nor_gate port map(c,d,k);

l14: nor_gate port map(e,f,l);

l15: nor_gate port map(g,h,m);

l16: nor_gate port map(i,j,n);

l17: or_gate port map(o,p,u);

l18: rsflipflop port map(k,q,u,qa,qa1);

l19: rsflipflop port map(l,r,u,qb,qb1);

l20: rsflipflop port map(m,s,u,qc,qc1);

l21: rsflipflop port map(n,t,u,qd,qd1);

l22: not_gate port map(k,q);

l23: not_gate port map(l,r);

l24: not_gate port map(m,s);

l25: not_gate port map(n,t);

end arch_shiftregister;