d flipflop behavoiral

library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (
d,clk,rd,sd : in STD_LOGIC;
q ,q1: inout STD_LOGIC);
end dff;
architecture dffarch of dff is
begin
process(d,clk)
begin
if (rd='1'and sd='0') then
q <= '1';q1<= '0';
elsif (rd='0'and sd='1') then
q <= '0';q1<= '1';
elsif (sd='0'and rd='0')then
q<='1';q1<='1'; end if;
if (sd='1'and rd='1')then
if clk'event and clk='1' then
q <= d ;q1 <= not d;
end if;
end if;
end process;
end dffarch;