Multiplexer

library ieee;

use ieee.std_logic_1164.all;

Entity eightone is

port(EN1,d1,d2,d3,d4,d5,d6,d7,d8,s0,s1,s2:in std_logic;

y:inout std_logic;

y_l:out std_logic);

end eightone;

architecture arch_eight of eightone is

signal m,n,l,en,y0,y1,y2,y3,y4,y5,y6,y7:std_logic;

component fiveand_gate

port(a,b,c,d,e :in std_logic;f:out std_logic);

end component;

component not_gate

port(a :in std_logic;b:out std_logic);

end component;

component eightnorgate

port(a,b,c,d,e,f,h,i :in std_logic;g:out std_logic);

end component;

begin

l1: not_gate port map(s0,l);

l2: not_gate port map(s1,m);

l3: not_gate port map(s2,n);

l4: not_gate port map(EN1,en);

l6: fiveand_gate port map(m,d1,n,l,en,y0);

l7: fiveand_gate port map(m,d2,n,l,en,y1);

l8: fiveand_gate port map(m,d3,s0,s1,en,y2);

l9: fiveand_gate port map(m,d4,s0,s1,en,y3);

l10: fiveand_gate port map(d5,s2,l,m,en,y4);

l11: fiveand_gate port map(d6,s2,l,m,en,y5);

l12: fiveand_gate port map(d7,s0,s2,l,en,y6);

l13: fiveand_gate port map(d8,s0,s1,s2,en,y7);

l14: eightnorgate port map(y0,y1,y2,y3,y4,y5,y6,y7,y);

l15: not_gate port map(y,y_l);

end arch_eight;