3-8 decoder

library ieee;

use ieee.std_logic_1164.all;

Entity three_eight is

port(A,B,C,E1,E2,E3:in std_logic;y0,y1,y2,y3,y4,y5,y6,y7:out std_logic);

end three_eight;

architecture decoder of three_eight is

signal g,f,n,j,i,h,m,l,k:std_logic;

component not_gate

port(a:in std_logic; b: out std_logic);

end component;

component fouripnand_gate

port(a,b,c,d:in std_logic; e:out std_logic);

end component;

component threeipand_gate

port(a,b,c :in std_logic;d:out std_logic);

end component;

begin

l1: not_gate port map(E2,g);

l2: not_gate port map(E2,f);

l3: not_gate port map(A,j);

l4: not_gate port map(B,i);

l5: not_gate port map(C,h);

l6: not_gate port map(j,m);

l7: not_gate port map(i,l);

l8: not_gate port map(h,k);

l9: threeipand_gate port map(E1,g,f,n);

l10: fouripnand_gate port map(n,h,i,j,y0);

l11: fouripnand_gate port map(i,h,m,n,y1);

l12: fouripnand_gate port map(n,h,l,j,y2);

l13: fouripnand_gate port map(h,m,l,n,y3);

l14: fouripnand_gate port map(j,i,k,n,y4);

l15: fouripnand_gate port map(i,k,m,n,y5);

l16: fouripnand_gate port map(i,j,k,n,y6);

l17: fouripnand_gate port map(n,l,k,m,y7);

end decoder;