dflipflop

library ieee;

use ieee.std_logic_1164.all;

Entity dflipflop is

port(SD,Rd,CD,D:in std_logic;

q0,q1: inout std_logic);

end dflipflop;

architecture arch_d of dflipflop is

signal a,b,c,e:std_logic;

component threeipnand_gate

port(a,b,c :in std_logic;d:out std_logic);

end component;

begin

l1: threeipnand_gate port map(SD,e,b,a);

l2: threeipnand_gate port map(a,RD,CD,b);

l3: threeipnand_gate port map(b,CD,e,c);

l4: threeipnand_gate port map(c,RD,D,e);

l5: threeipnand_gate port map(SD,b,q1,q0);

l6: threeipnand_gate port map(q0,RD,c,q1);

end arch_d;