rs flip flop

library ieee;

use ieee.std_logic_1164.all;

entity rsflipflop is

port(r,s,clk:in std_logic;

q,q1:inout std_logic);

end rsflipflop;

architecture archi_rs of rsflipflop is

begin

process(clk)

begin

if(clk 'event and clk='1')then

if(r='0' and s='0') then q<=q;q1<=(not q);

else if(r='0' and s='1') then q<='1';q1<='0';

else if(r='1' and s='0') then q<='0';q1<='1';

else if(r='1' and s='1') then q<='0';q1<='0';

end if;

end if;

end if;

end if;

end if;

end process;

end archi_rs;